The problem statement and a brief theoretical description of phase-locked loops is given in the next section. A walk-through of the source code follows. Wireless communications systems modulate the data signal with a high-frequency carrier before transmitting over the air.
For many modulation schemes the receiver's oscillator needs to be locked in phase to that of the transmitter; however, in practice there is a small bit of residual carrier offset between the two.
As its name implies, a phase-locked loop PLL is designed to lock the phase of an oscillator to the phase of a reference signal, providing a mechanism for synchronization on different platforms. In this example our input signal will be simply a complex sinusoid without noise or modulated information.
There are many types of phase-locked loops: digital e. What we are designing here is really the digital equivalent of an analog PLL using digital signal processing rather than soldering together a circuit with discrete components. While the end result will be a discrete-time system, we will first design the PLL in the analog domain and then convert it to its digital counterpart. In general the phase error detector simply computes the difference between the input and estimated phases while the loop filter removes much of the noise and tracks to the time-varying input phase.
There are several possibilities, but for this example we will use the active "proportional plus integration" PI which has a loop filter. This yields a closed-loop phase-locked loop transfer function:. Full digital phase-locked loop.
While I have provided a copy of the source code at the top of this document, you may simply download a tarball that includes the following files:. The program initially sets the parameters for the simulation, including the carrier phase and frequency offsets, the phase-locked loop filter specifications, and the number of samples to run. Initializing the variables to describe the loop filter can be a bit tricky.
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